1. Field of the Invention
This invention relates to a logic circuit, and more particularly to a logic circuit which is constituted from a collector dot AND circuit and a latched comparator circuit.
2. Description of the Prior Art
Various logic circuits have conventionally been put into practical use which is constituted from a combination of an AND circuit which receives a plurality of input signals such as a first input signal A and a second input signal B and outputs a logic AND of such input signals with a latched comparator circuit.
An exemplary one of such conventional logic circuits is shown in FIG. 2. The logic circuit shown is constituted from a modified AND circuit of OR and a latched comparator circuit in combination and has a first input terminal 1 and a second input terminal 2. The logic circuit receives, at the first and second input terminals 1 and 2 thereof, input NOT signals AN and BN of first and second input signals A and B. respectively.
An input NOT signal AN of a first input signal A received at the first input terminal 1 of the logic circuit is provided to the base of a transistor Q1. Meanwhile, another input NOT signal BN of a second input signal B received at the second input terminal 2 is provided to the base of another transistor Q3. The emitters of the transistors Q1 and Q3 and a further transistor Q4, to which a reference signal VREF1 is provided, are connected commonly such that a first differential circuit may be constituted from the transistors Q1, Q3 and Q4. A second differential circuit is constituted from transistors Q5 and Q7 and provided at a next stage to the first differential circuit. A third differential circuit is provided in order to selectively operate the first and second differential circuits. The third differential circuit includes a transistor Q2 to the collector of which the commonly connected emitters of the first differential circuit are connected. The third differential circuit further includes another transistor Q6 to the collector of which the commonly connected emitters of the second differential circuit are connected.
A clock signal CLK is provided to the base of the transistor Q6 while a NOT signal CLKN of the clock signal CLK is provided to the base of the transistor Q2, and the emitters of the transistors Q2 and Q6 are connected commonly and grounded by way of a constant-current source 20. A series circuit of a transistor Q8 and a constant-current source 21 and another series circuit of another transistor Q9 and another constant-current source 22 are connected in parallel to the first to third differential circuits, that is, between a power source Vcc and the ground GND. Each of the two series circuits constitutes an emitter follower for developing a logic level signal, and the collectors of the transistors Q1, Q3 and Q5 are connected to the base of the transistor Q8 while the base of the transistor Q7 is connected to the emitter of the transistor Q8.
Meanwhile, the collectors of the transistors Q4 and Q7 are connected to the base of the transistor Q9 while the base of the transistor Q5 is connected to the emitter of the transistor Q9. Thus, a signal outputted from the emitter of the transistor Q8 is led out to a first output terminal 11 of the logic circuit as an AND output signal A.multidot.B of a first input signal A and a second input signal B while a signal outputted from the emitter of the transistor Q9 is led out to a second output terminal 12 as an inverted AND output signal A.multidot.B of the first input signal A and the second input signal B.
A resistor R1 is connected between the collector of the transistor Q1 and the power source Vcc while another resistor R2 is connected between the collector of the transistor Q4 and the power source Vcc.
Subsequently, operation of the logic circuit of FIG. 2 having such construction as described above will be described. It is to be noted that the following description proceeds on the assumption that the logic circuit does not include the transistor Q1 and does not receive a first input signal A in order to facilitate the description. Where the transistor Q1 is omitted in this manner, the logic circuit of FIG. 2 operates in a quite similar manner as an ordinary latched comparator circuit.
In the logic circuit of FIG. 2, when the NOT signal CLKN of a clock signal CLK is "H" (high), an electric current I1 flowing through the constant-current source 20 flows only through the transistor Q2 but does not flow through the transistor Q6. Accordingly, no electric current flows through either of the transistors Q5 and Q7 which constitute the second differential circuit, and the electric current I1 flows only either one of the transistors Q3 and Q4. In this instance, the electric current I1 flows in response to magnitudes of an input NOT signal BN and a reference signal VREF1, and when the difference in voltage between the two signals BN and VREF1 is great, the electric current I1 flows only through the transistor Q3 or Q4. However, when the difference in voltage is small, electric currents flow through the transistors Q3 and Q4 in accordance with magnitudes of the voltages of the signals BN and VREF1.
In this instance, since the resistance of the collector of the transistor Q3 is provided by the resistor R1 and the resistance of the collector of the transistor Q4 is provided by the resistor R2, voltage drops take place across the resistors R1 and R2 in accordance with magnitudes of the electric currents from the collectors of the transistors Q3 and Q4, respectively. Accordingly, if the input NOT signal BN is a little higher than the reference signal VREF1, a higher electric current will flow through the transistor Q3, and accordingly, a voltage value at the collector of the transistor Q3 will be a little lower than a voltage value at the collector of the transistor Q4. It is assumed here that, in such condition, the NOT signal CLKN of the clock signal CLKN is changed into "L" (low). Consequently, an electric current begins to flow through the transistor Q6 while the electric current which has flowed through the transistor Q2 till then is stopped, and also the electric currents which have flowed through the transistors Q3 and Q4 are stopped.
When an electric current begins to flow through the transistor Q6, also electric currents begin to flow through the transistors Q5 and Q7. In this instance, since the collector of the transistor Q4 is "H", the base of the transistor Q9 and the collector of the transistor Q7 are "H". On the other hand, since the collector of the transistor Q3 is "L", the base of the transistor Q8 and the collector of the transistor Q5 are "L". Accordingly, the base of the transistor Q7 presents "L" while the base of the transistor Q5 presents "H". Consequently, at an instant when the clock signal CLK is changed into "H", a little higher electric current will flow through the transistor Q5 while an electric current flowing through the resistor R1 tends to increase a little. Consequently, the electric current of the collector of the transistor Q7 will be decreased reversely, and the voltage at the resistor R2, which has formerly been "H", varies so as to become further higher. In other words, the potential at the resistor R2 which has been "H" tends to further become higher while the potential at the resistor R1 which has been "L" tends to further become lower. Since such voltages are provided to the bases of the transistors Q8 and Q9, positive feedback is repeated among the transistors described above. Consequently, a difference in voltage which has been a little between the input NOT signal BN and the reference signal VREF1 is amplified by a comparator mode and a positive feedback mode is entered at an instant when the clock signal CLK is reversed to "H", and an "H" level and an "L" level are distinguished clearly. In particular, the logic circuit effects an analog operation in a comparator mode but effects a digital operation in a positive feedback mode. As the logic circuit operates in this manner, an AND output signal A.multidot.B is led out to the first output terminal 11 of the logic circuit while an inverted AND output signal A.multidot.B is led out to the second output terminal 12.
Since the logic circuit shown in FIG. 2 operates in such a manner as described above, signals to be supplied to the first and second input terminals 1 and 2 of the logic circuit must necessarily be input NOT signals, and accordingly, a NOT circuit must be provided at a preceding stage to each of the input terminals 1 and 2. Accordingly, there are drawbacks that some delay takes place with such input signal and circuit construction of the logic circuit is complicated as much.
Also logic circuits are conventionally known which do not require provision of such NOT circuits at a preceding stage as different from the logic circuit shown in FIG. 2. An exemplary one of such conventional logic circuits is shown in FIG. 3. Referring now to FIG. 3, the logic circuit shown is constituted from a combination of an AND circuit called cascade AND circuit and a latched comparator circuit and includes an AND circuit at a first stage including a first differential pair composed of transistors Q1 and Q4 and a second differential pair composed of transistors Q2 and Q5. In the case of the logic circuit of FIG. 3, a first input signal A supplied to a first input terminal 1 of the logic circuit is supplied to the base of the transistor Q1 constituting the first differential pair while a first reference signal VREF1 is supplied to the base of the transistor Q4. Meanwhile, a second input signal B supplied to a second input terminal 2 of the logic circuit is supplied to the base of the transistor Q2 while a second reference signal VREF2 is supplied to the base of the transistor Q5. And, a voltage at the collectors of the transistors Q4 and Q5 is supplied to the base of a transistor Q10 while another voltage at the collector of the transistor Q1 is supplied to another transistor Q9. Consequently, an AND output signal A.multidot.B is obtained from the emitter of the transistor Q10 while an inverted AND output signal A.multidot.B signal is obtained from the emitter of the transistor Q9. It is to be noted that construction and operation of the other portion part of the logic circuit of FIG. 3 are similar to those of the logic circuit of FIG. 2, and accordingly, overlapping description thereof is omitted herein to avoid redundancy.
The logic circuit of FIG. 3 is advantageous in that, since first and second input signals A and B can be inputted directly to the logic circuit as described hereinabove, NOT circuits need not be provided at a preceding stage. However, the logic circuit of FIG. 3 has a drawback that, since the level of the second input signal B must be lower by a predetermined level than that of the first input signal A, a level shifting circuit must be provided at a preceding stage.